Body is a clockchart. It is the basic unit of a module, or class. It normally contains states and events.
Candidate variables are those variables which are candidates to in a modules interface. They must be in the interface of a parent, a sibling or a child.
Classes are fully described bodies which can be instantiated by any module which doesn't yet possess a body.
Clockchart is an a fully described module whose body has an interface, events and states.
Clocks can be declared within a body. They are controlled by functions or events within the body. Every system has a global clock that must tick infinitely often. When the tick event is taken, all event timers and clocks advance in lock-step with the tick.
Controller is a term used to denote the machine of a real-time system.
Control variable is a variable that differentiates the states in a give module.
Event is a transition between two states. Each event has an associated event timer. The event timer is used to insure that the event is taken somewhere between its lower and upper time bounds. Events also have guards; the guard must be true before an event can be taken. Also events have functions, or actions, that which are invoked when the event is taken.
Environment of a given module is the external interface with the module. When your project is compete, with a machine and an appilcation domain, the environment of any module is determined by the project. However when you creating your project the environment of new modules can be created using the simulation tool of stateclock.
Interface is a list of variables each of which has a mode; in, out or share. The body can read an in variable, but only the environment can write to it. The environment can read an out but only the body can write to it. Both the body and the environment can write to a share variable.
Module can be the parent of one or more sub modules, it can be instantiated from a class, or it might consist of a body.
Plant is a term used to denote the application domain of a real-time system.
Primitive objects are initially declared states. These state objects are not indivisible, however.
Project is a stateclock system of one or more modules.
Specification is a set of temporal logic formulas in the interface variables. The specification describes how the module should behave in an arbitrary environment.
StateClock is a tool for constructing systems of reactive modules, executing the system( or parts of it), and verifying the system compositionally ( module by module).
STeP is a theorem prover and a model checker. You can submit your specification file and your fts file to STeP and use modelchecker to determine whether the requirements are satisfied.
XOR tells stateclock that states you are about to create will be serial in their execution. Think of them executing in a single thread of execution.