Getting Started with PCB

Getting Started with PCB
Written by Christopher Thomas.

Table of Contents

Building PCB
Important Operations
Idiosyncracies
Using PCB in the VISOR Lab

Building PCB

In theory:

Download the most recent release from PCB's SourceForge page.
Unpack it into a working directory.
Use "./configure" to set up the makefiles. I use "--PREFIX=/(my home directory)/approot" to install it into a userland application tree. Do whatever you're used to.
Use "make" to build it, and "make install" to install it.
Type "pcb" to test it.

In practice:

You're probably going to be missing dependencies (other projects or utilities PCB depends on). Recurse to download and build these.
Unless you're doing this at home as root, you'll need your own local applications tree. Use the "--PREFIX" option to tell "configure" where it is.
You're probably going to be forgetting to create some of the directories PCB expects to put things in the local applications tree. It'll fail the first time it installs, complaining about this. Make them and try again.
The most important directory after installation is the "newlib" directory, at (approot)/share/pcb/newlib. This is where PCB puts user-created library elements. After setting up PCB, any in-house library directories your lab has can go under here.

Important Operations

Things you'll be doing quite often in PCB:

Adjusting active sizes.

This is a menu option, which lets you change trace and via sizes.
Creating instances of "elements" (PCB objects which contain named vias, wiring, and silkscreening).

To do this, use "file"->"load element data into buffer", then select the "buffer" tool to paste copies of it.
Placing vias, drawing wires, drawing text, and drawing rectangle or polygon fills.

The tools for this are pretty self-explanatory. Text is usually drawn in the silkscreen layer, though using the metal layers may be needed if you're not prototyping with silkscreens.

Polygons only fill in if you end exactly where you started.
Creating "therms".

These are X-shaped wire patterns that connect vias to surrounding fill. They're mostly used to connect ground lines to the ground plane.
Grouping design components into "elements".
1. Number all of the vias in the soon-to-be-element. Do this by giving them names that are pin numbers (select the desired via, and press "n").
2. Select all of the components.
3. Carefully bring up the pop-up menu by right-clicking at exactly the location you want to be the element's local zero point.
4. Select "group components into element" from the pop-up menu.
5. Use the "q" key to toggle squareness of vias and pads.
6. Give descriptive names to pins/pads (these are distinct from the via names you previously gave).
7. Select the element.
8. Bring up the pop-up menu again, at the desired zero location.
9. Select "copy element to buffer" from the pop-up menu.
10. From the buffer menu, select "save buffer elements to file".
11. Load the saved element data to the buffer, and create a new element instance, to make sure it worked as desired.
As long as there's at least one element in the selected items being cut to the buffer, the whole buffer gets saved. This is how you save fills, which normally aren't cut into the element.

Idiosyncracies

Oddities of PCB, in no particular order:

The sizes the "via size" and "hole size" sliders will jump to depend on each other. If you want a 35-mil hole and are only being allowed 34 and 36 mils, tweak the via size, set the desired hole size, then move the via size back.
The "board size" sliders won't ever give you integer values. Set to slightly larger than you need, exit the program, then hand-edit the design file in a text editor to specify the desired board size (it's right near the top). Be warned that anything cropped due to reducing the board size may vanish from the design.
Wires sometimes go orthogonally and then at 45 degree angles, and sometimes the reverse. This alternates every time you lay a wire down. You can switch to the opposite orientation by holding down the Shift key.
Polygon and rectangle fills only avoid vias if the center of the via is inside the fill. Make sure this is the case; otherwise you'll make contact without intending to.
Vias have two names when they're part of an element - their name as a via, and their name as a pin in the element. The via name should be the pin number, and the element pin name a descriptive name.
Polygon fills, rectangles, and so forth aren't saved in elements. Pins, pads, silkscreen lines, and silkscreen text are. However, you can save everything in a selected design block from the buffer menu as long as at least one element is present in the buffer.
Only pins and pads in elements have solder mask cutouts. Make any vias that will connect to components, parts of elements. Vias that aren't parts of elements should either be mounting holes or vias that strap traces between layers.

Using PCB in the VISOR Lab

These notes are intended for students in the Vision Sensor Laboratory at York University who use the PCB software package.

You'll have to create a local applications directory tree. We don't have root access.
We have pre-existing component libraries. Copy them into the "newlib" directory.
We have lots of documentation on designing useful PCBs, and on the pinouts for standard experiment chips. Read this documentation.
Please make sure mounting holes are compatible with standard screws (4-40, 6-32, and rarely 1/4-20). Please also make sure mounting hole spacing is either an integer number of inches, or at least a multiple of 0.25". This makes it much easier to make the thing the board attaches to.
We fabricate using Alberta Printed Circuits. This adds a few constraints:
- They have specific drill sizes they use. When possible, use the free ones.
- Design with hole size being the real, unplated hole size (i.e., the drill bit size). Specify this when submitting the design, so your holes are the size desired.
- Assume the holes you get back will be at least 5 mils narrower. Make designed holes 5-10 mils wider than the component leads to compensate.
- We don't normally get the silkscreened process. Put any writing, pin-1 identifiers, and so forth on the metal layers.
- Keep traces at least 10 mils thick and 10 mils apart. In theory APC can give us finer pitches, but don't count on it.
- Check APC's site for instructions on submitting a design.

Written by Christopher Thomas. Last updated 08 May 2006.