Memory Design Problem

Assume you are designing memory hardware for a new CPU. The memory addressing will have segments that are paged. The machine has a 64-bit logical memory address. Each process can have up to 64K (65536) segments, and page size is 64K bytes. The segment tables (ST) and page tables (PT) are stored in main memory. Each segment table entry (STE) points to a page table. Each page table entry (PTE) includes a pointer pointing to a page in real memory. Each PTE will also have: a "read-enable" bit, a "write-enable" bit, a "valid-invalid" bit and a bit that is set on each reference to the page. The machine will support physical memories up to 64 gigabytes.

· Draw a diagram of memory mapping according to your design. Show how the pieces of the virtual address are used to reference each of the tables, and how to generate the physical address. Indicate the size of each field, where it comes from, and where it is used.

· How large (in bytes) is a full-sized ST in your design?

This is a design problem. We do not expect a unique solution. Please base on the basic principles in class and make your design as reasonable as you can.