• FROM THE TA:

1. Detailed schematic circuit diagrams, including pin and chip numbers,
power supply etc.
2. Layout and wiring diagrams showing in detail how was the circuit
assembled on the lab station, lights and switches used etc.
3. Testing strategy, including test patterns used.
4. List of parts used.
5. Truth tables and maps.
6. A data sheet summary of each major chip used (e.g., multiplexers,
decoders, adders), including typical applications, truth tables, timing
diagrams, etc.
7. Date on which lab was completed.

• The lab contains 5 parts. Parts A, B and C are design problems to be implemented and demonstrated in the lab. All parts are to be included with your laboratory report but part D and E are not to be implemented. HAND IN EITHER PART D OR PART E BUT NOT BOTH.

• Before entering the lab ensure that for each design you have at a minimum: tables, maps and other design aids, a fully documented schematic (neatly hand drawn is fine but include chip and pin numbers), layout, parts list and testing plan.

• If you are not prepared for the lab you will not be allowed to start. The three hour lab time slots are strictly enforced and you must be prepared in order to complete the lab in the allotted time.

• The implemented circuits must be demonstrated to the TA who will note a completed lab. When implementing the circuit be sure to use the switches and lights to make it easy to demonstrate your circuits.

• A brief, concise lab report describing your designs and the implemented circuits (include a functional description of the circuit with enough detail that someone else could easily use your circuit) is required on the Friday of the last week of each lab.

• Try sites like http://www.fairchildsemi.com/catalog/Digital.html or http://www.ti.com/sc/docs/asl/home.htm for datasheets

• Ensure selected parts are on the list of available items

Construct a level sensitive J-K flip flop using NAND gates.  Determine the behaviour of the circuit for all possible combinations of the inputs. Using the logic and data switches on the tester (to create the clock pulse and inputs) determine what happens when the clock pulse is extended. Convert your circuit into a master slave version (hint one circuit should suffice for both of these designs with minor wiring changes). Draw a timing diagram (before the lab) predicting the values of the outputs of each stage for the following sequence of JK inputs (synchronous with the clock) 01, 11, 11, 10, 00, 00, 11. Compare your predicted pattern with the actual behaviour of the circuit.

PART B Gray Code Counter

Construct a counter to count up in three bit Gray code (see page 21 of Mano) using standard sequential logic techniques and JK flip flops. For the report only, design an equivalent circuit using 7474 flip-flops and compare the designs.

PART C Pseudo-Random Sequence Generator

A pseudo-random sequence is a sequence of bits (bit stream) which approximates a randomly distributed binary variable. The sequence is apparently random but repeats at a regular interval (usually a large interval). These circuits are useful in a variety of applications (toys, communications, cryptography, test equipment ...). Build a six flip-flop pseudo-random sequence generator using 7474  D flip flops (we also have a limited supply of 74175 quad D-type but you will be limited in ability to preset). This circuit has the output of stage one connected to the input of stage 2 and so on, as in a shift register. The input to the first flip-flop is the output of the fifth and sixth flops XORed together. Start the sequence with a given code by connecting the preset and clear inputs appropriately (connect them to a switch which can be momentarily closed to reset the . What is the length of the pseudo random sequence (hint to find the trend a two, three and four stage generator have the following outputs XORed respectively for the input to stage1: 1&2, 2&3 and 3&4)? Are any states problematic?

For the report only, design a nine stage pseudo random sequence generator (outputs 5 and 9 XORed) using a 74164 shift register and other logic. Include a control inputs to shift in a given pattern directly (known as the seed) over nine clock cycles.

PART D Shift Registers and Serial Code Converter

i) This question was taken from page 463 of Mano. Design but do not implement a four bit bi-directional shift register with parallel load using a 74195 shift register and a 74157 multiplexor. The circuit should be able to perform shift left and right, parallel load and both synchronous and asynchronous clear. Document your design and provide a functional description.

ii) A n-bit parallel binary to gray code converter works as follows: output bit 0 is the XOR of the inputs 0 and 1,  output bit 1 is the XOR of the inputs 1 and 2, ...  output bit n-1 is the XOR of the inputs n-1 and n, output n is simply input n. Design a serial version of this convertor to convert an n-bit binary number to a gray code number starting with the most significant bit. Use a JK flip-flop, and an XOR gate to perform the conversion along with a switch to reset and start the conversion (note that a flip-flop can act as a one bit delay). Concern yourself primarily with the data conversion - assume that the output serial stream is stored in a serial-in parallel-out shift register and that external counter/sequencer circuitry gates the clock off after all n bits have been converted.

OR, OR, OR, OR (postulate 0: four ORs don't make an AND)

PART E Counters

i) Design (but do not implement), using ********* 74161 counters and other logic as necessary, a mod 10 counter that counts up 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 and then restarts at 0011 or counts down in the reverse order. Up/down direction is controlled by an input and the circuit has an input for synchronous resetting or loading to initialize to a known count. Document your design.

ii) Compare the speed of a four bit ripple counter design based on 7476 JK flip-flops with a four bit synchronous counter using the 7476 and any other logic you require. What is the maximum clocking rate for each circuit? Can you explain how a ripple counter can easily (trivially) be used as a frequency divider?