EECS 2021

Computer Organization


Syllabus
Notes
Notices
Dates
Labs
FAQs
Contact Info
Marks
Last Modified:
Sep 6 2023

Course Description


In this course we will discuss the core concepts of computer organization. We will examine concepts related to both hardware (gates, memory, binary system, etc) and software (compilers, assemblers, etc) and of course their interface. We will introduce and use in the lab assignments two important tools in this course: assembly programming (we use RISC-V) and hardware programming (we use Verilog). By the end of the course students will be able to:
  • Translate high-level code to assembly language and machine code.
  • Represent data in machine readable form and describe how it is stored and manipulated in a CPU.
  • Synthesize hardware of increasing complexity from logic gates to a simple CPU using a Hardware Description Language.
  • Evaluate computer performance and compare performance on different architectures and designs.
  • Describe and analyze I/O and Parallel Hardware.
  • Lecture Hours

    Day Time Room Zoom link
    Mon.11:30am DB 0016 Zoom
    Wed.11:30am CLH G Zoom

    All lectures are in person but will be recorded and made available for you on eclass (Moodle). If you cannot attend you can connect through Zoom. It is strongly recommended to attend the lectures in real time but if you have time conflict during the time slot, it is strogly recommended to watch the video shortly afterwards and before the labs.

    Tests

    There will be a midterm worth 25% and a final worth 30%. The final will cover all the material in the course and will be during the regular exam period.

    Labs.

    There will be four RISC-V assembly lab assignments carrying in total 14% of the final mark. These will be during the prescheduled labs. The three best labs will count. The programming components of the labs are marked by the TAs at the end of the lab session and you get either pass or fail. The marking will be based on effort and correctness. If you come on time and do not leave early, a partailly correct submission will give you the marks. If you come late, or want to leave early the submission has to be correct. If you miss a lab you get a fail for this lab. Missing only one lab will not directly affect your final mark for the course (since the best three out of the four count) but missing more than that, will. There will be TAs and the instructor available in person during the lab, and you can ask them for hints and guidance for the programming part of the lab. Also the TAs or the instructor can ask to review your work so far and offer help.

    Similarly, there will be four Verilog lab assignments carrying in total 16% of the final mark. Marking will be based on effort and correctness. But weighted more heavily on correctness. Like the assembly the three best count.

    The regular labs may include a multiple choice quiz that will carry 50% of the lab assignment mark. If for example you complete and submit the programming assignment and receive 80% on the quiz the mark for this lab will be 90%.

    There will be one labtest after the first four regular assembly lab which carries 15%. The labtests are conducted in a similar manner but the TAs and the instructor will only answer clarification questions.

    You prepare for the labs by studying the material for the labs in this site. Make sure you study the lab for the week, the user manual, the assembler manual and system calls manual

    If you complete the regular lab early, you ask a TA or the instructor to review the programming component and record the result. Then you can log out. Otherwise submit your work just before the end of the session and it will be marked by the TAs. If you put an honest effort (ie, came on time, did not leave early, and the submitted solution is on the right track) you may still get a good mark for this lab assignment.

    Text

    The text is "Computer Organization and Design: The Hardware/Software Interface" by David A. Patterson, John L. Hennessy RISC-V edition.

    Last Modified: Sep 6 2023